The present invention relates generally to semi-conducting manufacturing, and more particularly to deposition of copper for integrated circuit interconnects.
In the field of semiconductors, the materials used to make interconnects and fill the windows, or vias, must have both low resistivity and the ability to withstand volatile process environments. Aluminum and tungsten materials are often used in the production of ICs for making interconnections or vias between electrically active areas. These metals are popular because they are easy to use in a production environment, unlike copper which requires special handling. The integrated circuit (IC) industry is currently researching and developing new metallic interconnect materials and structures that can be used with integrated circuits. One promising material for use in IC interconnects is copper.
Copper is a natural choice to replace aluminum in the effort to reduce size of lines and vias in an electrical circuit. The conductivity of copper is approximately twice that of aluminum and over three times that of tungsten. As a result, the same circuit can be carried through a copper line having half the width of the aluminum line. The electro-migration characteristics of copper also are superior to aluminum. Copper is approximately ten times better than aluminum with respect to electromigration. Therefore, a copper line having a smaller cross-section than an aluminum counterpart would still be better able to maintain electrical integrity.
However, processing limitations with regard to copper must be solved before copper replaces aluminum in IC technology. For example, copper pollutes many materials used in IC processes and, therefore, more care must be taken to keep copper from migrating. The migration of copper into silicon semiconductor regions is especially harmful to optimum semiconductor performance and useful life. The conductive characteristics of the semiconductor regions are a consideration in the design of transistors. Typically, the fabrication process is carefully controlled to produce semiconductor regions in accordance with the design. Elements of copper migrating into the semiconductor regions can dramatically alter the conductive characteristic of the associated product. Various methods have been suggested to deal with the problem of copper diffusion into integrated circuit materials. Several materials, especially metallic materials, such as molybdenum and titanium nitride, have been suggested for use as barriers to prevent copper diffusion problems.
Further, there is currently no known technology which can plasma etch or wet etch copper materials. However, functional copper interconnects must be adequately provided over the surface of an integrated circuit. To overcome this limitation, copper chemical mechanical polishing (CMP) is one promising alternative that may facilitate the use of copper in the IC industry.
A further problem with copper relates to its willingness to oxidize and otherwise corrode to a much greater degree than its aluminum counterpart. To delay or control this oxidation, a thin layer of oxide has been placed at the surface of the copper plugs that are deposited within a via. To provide a clean and uniform copper surface, CMP processes are then used to remove the oxide layer. However, problems have surfaced with regard to the uniformity of the finished surface layers since precise removal of layers, such as an oxide layer, from a softer material, such as copper, presents special difficulties. In other words, the CMP processes currently contemplated for use with copper technology does not allow for the uniform removal of an oxide surface layer. In any event, the deposition of an oxide layer after the copper deposition results in an additional, time-consuming process step for the manufacture of copper interconnects.
The present invention is therefore directed to a method of providing an oxide layer in situ during the deposition of a copper-containing layer. One preferred embodiment is directed to a method of forming a semiconductor by providing a substrate having a metallic interconnect. A dielectric layer is formed on the substrate. Vias are etched or otherwise machined into the semiconductor to establish interconnects. Copper is deposited into the via such that an oxide layer is codeposited within the copper in the via in situ. An additional amount of copper is then deposited to cover the oxide layer. Optional barrier layers and other compatibilizing layers may be deposited into the vias prior to depositing the copper plug.
A further embodiment of the present invention is directed to a semiconductor comprising copper interconnects having oxide layers deposited within the copper in situ.
In a still further embodiment, the present invention is directed to a semiconductor comprising a substrate with a dielectric layer formed on the substrate. Vias are formed in the dielectric layer and made to extend through the dielectric layer. Optionally, barrier layers coat the walls and floor of the via followed by the deposition a copper-containing material into the via, with at least one oxide layer formed in the copper layer in situ. Additional copper is then deposited to cover the oxide layer.